Manufacturing method of multilayer semiconductor device

積層型半導体装置の製造方法

Abstract

【課題】上段側半導体素子の一部が下段側半導体素子の外周より外側に突出する積層構造において、素子間隔が狭い積層構造を実現しつつ、上段側半導体素子の載置時や接着剤の硬化処理時におけるチップシフトを抑制する。 【解決手段】配線基板2上に搭載された第1の半導体素子5上に、低回転時粘度μ 0.5rpm )が10〜150Pa・sの範囲であると共に、高回転時粘度μ 5rpm に対する低回転時粘度μ 0.5rpm の比で表されるチキソ比(μ 0.5rpm /μ 5rpm )が2以上の接着剤を介して、第1の半導体素子5の外周より外側に突出した部分を備える第2の半導体素子9を配置する。第2の半導体素子9の突出部分9aと配線基板2との間の中空部に接着剤を充填しつつ、第2の半導体素子9を第1の半導体素子5上に接着する。 【選択図】図2
<P>PROBLEM TO BE SOLVED: To suppress chip shifts at mounting a semiconductor element on the upper side and at curing for adhesive agent while acquiring a laminate structure having narrow element spacing, in the laminate structure which protrudes projected a part of a semiconductor element in the upper side outward from the periphery of a semiconductor element in the lower side. <P>SOLUTION: A second semiconductor element 9 having a portion protruding outward from the periphery of a firs semiconductor element 5 is arranged on the first semiconductor element 5 mounted on a wiring board 2 via the adhesive agent whose viscosity at low-speed rotating μ<SB>0.5 rpm</SB>is in the range of 10-150 Pa s, and thixo ratio (μ<SB>0.5 rpm</SB>/μ<SB>5 rpm</SB>) represented by a ratio of a viscosity at low-speed rotating μ<SB>0.5 rpm</SB>to a viscosity at high-speed rotating μ<SB>5 rpm</SB>is two or more. While a hollow part between a protrusion 9a of the second semiconductor element 9 and the wiring board 2 is charged with the adhesive agent, the second semiconductor element 9 is bonded on the first semiconductor element 5. <P>COPYRIGHT: (C)2010,JPO&INPIT

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Patent Citations (1)

    Publication numberPublication dateAssigneeTitle
    JP-2007324443-ADecember 13, 2007Toshiba Corp, 株式会社東芝Multilayer semiconductor device and production method thereof

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Cited By (1)

    Publication numberPublication dateAssigneeTitle
    JP-2012124423-AJune 28, 2012Toshiba Corp, 株式会社東芝Manufacturing method, manufacturing program, and manufacturing apparatus of semiconductor device