DTCMOS circuit having improved speed

Abstract

A DTCMOS circuit produces an output based on a logical combination of input logic signals. The circuit includes input transistors which receive on a respective gate a respective logic signal. The transistors have a body contact which is connected to the gate of another transistor. Transistors which are receiving later arriving logic signals therefore have a threshold voltage lowered by an earlier arriving logic signal. By coupling the earlier arriving logic signal with a body contact of another input transistor, the threshold voltage may be lowered prior to processing of the subsequently arriving logic signal. The DTCMOS circuit may be implemented in SOI with the attendant benefits of a lower supply made possible by the lowered voltage threshold each of the transistors without sacrificing leakage current inherent in DTCMOS circuits.

Claims

What is claimed is: 1. A logic circuit comprising: a plurality of inputs for receiving individual logic signals; DTCMOS circuit connected to receive said inputs and to provide an output which is the logical combination of said logic signals, said circuit having a plurality of input transistors which receive on a gate thereof respective logic signals, at least one of said transistors having a body contact connected to a gate of another transistor, whereby said at least one transistor which receive a later arriving logic signal has a threshold voltage lowered by an earlier arriving logic signal which is received on its body contact. 2. The logic circuit according to claim 1 wherein said input transistors are connected in a stack. 3. The logic circuit according to claim 2 wherein said input transistors have source drain connections serially connected together between terminals of a supply voltage. 4. The logic circuit according to claim 3 comprising three input transistors and an transistor having a source drain connection connected between a junction of a source and drain of two of said input transistors and to a terminal of said supply voltage, and having a gate connected to a gate of one of said input transistors. 5. The logic circuit according to claim 4 wherein said input transistor has a body contact connected to its gate. 6. A DTCMOS logic circuit for implementing a NAND function comprising: first, second and third transistors having a gate connected to receive first, second and third logic signals, respectively, and having a body contact connected to receive said third logic signal, said transistors having serially connected drain-source connections; a fourth transistor serially connecting said first, second and third transistors to a voltage supply; and fifth and sixth transistors having gate connections connected to receive said second and third logic signals and having a source-drain connection connected in parallel with said fourth transistor source-drain connection forming an output node for said logic circuit. 7. A method for increasing the speed of DTCMOS logic circuits comprising: connecting logic signals to gates of an input transistors, each of said input transistors having a body contact; and coupling an earlier arriving logic signal to a body of an input transistor receiving a later arriving logic signal; whereby the transistor receiving a later arriving signal has a lower threshold voltage. 8. The method according to clam 6 further comprising coupling the earliest arriving signal to the body contact of an additional transistor receiving an additional later arriving signal. 9. The method according to claim 6 further comprising connecting said input transistors in a stack to form a logic circuit for producing an output signal which is a logical combination of said logic signals.
BACKGROUND OF THE INVENTION The present invention relates to DTCMOS circuits which are implemented in SOI. Specifically, a circuit is described having a plurality of input transistors whose threshold voltage is controlled by an early arriving logic input signal. Dynamic threshold metal oxide semiconductor (DTMOS) devices can be fabricated on silicon-on insulator (SOI) substrates as described, for instance in U.S. Pat. No. 5,559,368. The SOI environment has offered the promise of reducing device sizes to the submicron gate level. The MOSFET devices are fabricated using a layer of semiconductor material deposited over an insulation layer of a supporting bulk wafer. The resulting structure includes a film of monocrystalline silicon on a buried layer of silicon oxide. The bulk silicon material from which the channel of the MOSFET device is formed is either grounded, or in many applications connected to the source region of the device. In accordance with the application described in the aforesaid referenced patent, the MOSFET device monocrystalline silicon film is connected to the gate of the MOSFET device to reduce the turn-on voltage (V t ) when the gate voltage is high. The reduced threshold voltage V t for the device improves its performance in numerous respects. When the FET is OFF, the threshold voltage is increased reducing subthreshold leakage currents. Applications which use DTCMOS devices provide not only the advantage of lower leakage currents while the MOSFET device is off, and lower threshold voltages when the device is on, but may also improve the speed of circuits utilizing MOSFET. The present invention is directed to one such application for improving the speed of DTCMOS logic circuits. SUMMARY OF THE INVENTION A DTCMOS circuit is implemented in SOI technology to perform a logical combination of input logic signals. The circuit includes a plurality of input transistors which receive on a gate thereof respective logic signals which are to be logically combined. The transistors formed in the SOI technology have a body contact connected to the monocrystalline silicon film of the device. Use is made of the body contact for controlling the voltage threshold V t of a device which receive a respective logic signal. In accordance with a preferred embodiment of the invention, an earlier arriving logic signal is coupled to the gate of one input transistor, as well as to the body contact of another transistor receiving a later arriving logic signal. A data transition on the earlier arriving logic signal will lower the voltage threshold of the input transistor receiving the later arriving signal. Thus, a dynamic lowering of the voltage threshold occurs permitting an increase in speed for the logic circuit. The DTCMOS circuit provides for the usual advantages of lower voltage thresholds and reduced power supply voltage requirements, as well as improves the speed for the circuit due to the lowering of the voltage threshold on input transistors which receive later arriving logic signals. DESCRIPTION OF THE DRAWINGS FIG. 1 is an illustration of a DTCMOSFET implemented in SOI technology; FIG. 2 illustrates a prior art DTCMOS inverter having gates tied to the body of each FET device; FIG. 3 illustrates a DTCMOS NAND gate; FIG. 4 illustrates a first embodiment of the invention which provides for a two-input NAND gate in accordance with the invention; and FIG. 5 illustrates a three-input NAND gate in accordance with a second embodiment of the invention. DESCRIPTION OF THE INVENTION FIG. 1 illustrates a cross-section of an SOI MOSFET having a body contact connected to the silicon 14 . The DTCMOS NFET is fabricated in SOI substrates 10 having a buried oxide layer 12 formed therein with a p-silicon film 14 on the buried oxide layer 12 . An n-source region 16 is provided, as well as a drain region 18 . A gate 20 is formed over the gate insulation 22 . A body connection 19 is made between the gate 20 and body 14 permitting the body potential to be controlled in response to an applied gate voltage. As is known from the prior art, the gate and body connection are connected together as is shown in FIGS. 2 and 3. The inverter circuit of FIG. 2 has a lower threshold voltage V t for each of the transistors 23 and 21 because the NFET 21 and PFET 23 have body contacts 22 and 24 connected to the gates of the respective device. A signal A applied to input 18 produces an inverted level represented by the voltage X at output 25 . The foregoing arrangement reduces the threshold (V t ) for each of the transistors 21 , 23 , when the FET is conducting. The foregoing principles of the prior art are also applied in a two-input NAND gate shown in FIG. 3 . The NAND gate includes a stack of transistors 32 and 33 serially connected so that the drain and sources of each transistor are connected in series with the output 34 . Transistor 31 is a PMOS transistor in parallel with PMOS transistor 36 . The body connections for each of the transistors are connected to their respective gates. Logic signals A and B are applied to input terminals 29 and 30 , as well as to the gate of transistor 36 . The NAND gate of FIG. 3 provides an output voltage X when input signals A and B are at a low, zero level. The circuit also has the advantage of a reduced V t for each of the transistors, thereby improving the overall circuit speed. FIG. 4 represents a first embodiment of the invention, wherein the body potential of a transistor is controlled by the input signal of an adjacent transistor. Transistors 41 , 42 and 43 are connected in a stack, source to drain, and the stack is in turn connected across the terminals of power supply Vdd. Logic signals A and B are applied to input terminals 39 and 40 , as well as to the gate of PMOS transistor 48 . Output terminal 50 provides a signal X which is the logical combination produced by a NAND gate. The circuit of FIG. 4 includes a transistor 42 in the stack of transistors having a body contact 45 which is connected to the gate of transistor 43 . The aforesaid connection permits the body of transistor 42 to be set at a high potential when logic signal B goes high. In this way, if logic signal B arrives ahead of logic signal A, the threshold V t of transistor 42 will have been lowered and transistor 42 will otherwise turn on sooner than had body contact 45 been connected to its gate. Accordingly, with the foregoing arrangement, when logic signal B is low, a higher threshold voltage is maintained on transistor 42 providing enhanced noise immunity, and reduced leakage currents. However, when the logic signal B goes to a high value, the threshold voltage for transistor 42 will be lowered. The same principle may be applied to the three-input NAND gate shown in FIG. 5 . Input terminals 51 , 52 and 53 receive logic signals A, B and C. Additionally, PMOS transistors 60 and 61 receive logic signals B and C as well. An output terminal 62 provides the logical output of the NAND function for input signals A, B and C. As is illustrated in FIG. 5, the body contact of transistors 56 , 57 and 58 is connected to the input terminal 53 . Each of these NFET devices when receiving a logic signal C provide a lower threshold voltage for the respective transistors 56 , 57 and 58 . Thus, if signals A and B arrive later than signal C, the threshold values for transistors 56 and 57 have already been reduced, effectively speeding up the generation of an output signal on terminal 62 . The lower voltage thresholds on each of the transistors means also that the power supply voltage Vdd may be correspondingly reduced as is beneficial in DTCMOS circuitry. The foregoing description of the invention illustrates and describes the present invention. Additionally, the disclosure shows and describes only the preferred embodiments of the invention, but as aforementioned, it is to be understood that the invention is capable of use in various other combinations, modifications, and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein, commensurate with the above teachings, and/or the skill or knowledge of the relevant art. The embodiments described hereinabove are further intended to explain best modes known of practicing the invention and to enable others skilled in the art to utilize the invention in such, or other, embodiments such as for NOR gates, AND gates, tribuffers, etc., and with the various modifications required by the particular applications or uses of the invention. Accordingly, the description is not intended to limit the invention to the form disclosed herein. Also, it is intended that the appended claims be construed to include alternative embodiments.

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Patent Citations (11)

    Publication numberPublication dateAssigneeTitle
    US-3737673-AJune 05, 1973Tokyo Shibaura Electric CoLogic circuit using complementary type insulated gate field effect transistors
    US-4122360-AOctober 24, 1978Tokyo Shibaura Electric Company, LimitedLogic circuit using CMOS transistors
    US-5461330-AOctober 24, 1995Digital Equipment CorporationBus settle time by using previous bus state to condition bus at all receiving locations
    US-5465054-ANovember 07, 1995Vivid Semiconductor, Inc.High voltage CMOS logic using low voltage CMOS process
    US-5467048-ANovember 14, 1995Fujitsu LimitedSemiconductor device with two series-connected complementary misfets of same conduction type
    US-5514982-AMay 07, 1996Harris CorporationLow noise logic family
    US-5559368-ASeptember 24, 1996The Regents Of The University Of CaliforniaDynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation
    US-5583454-ADecember 10, 1996Advanced Micro Devices, Inc.Programmable input/output driver circuit capable of operating at a variety of voltage levels and having a programmable pullup/pulldown function
    US-5729155-AMarch 17, 1998Nec CorporationHigh voltage CMOS circuit which protects the gate oxides from excessive voltages
    US-5748029-AMay 05, 1998Sgs-Thomson Microelectronics S.R.L.MOS transistor switching circuit without body effect
    US-6064263-AMay 16, 2000International Business Machines CorporationDTCMOS differential amplifier

NO-Patent Citations (0)

    Title

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    US-8970289-B1March 03, 2015Suvolta, Inc.Circuits and devices for generating bi-directional body bias voltages, and methods therefor
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    US-9838012-B2December 05, 2017Mie Fujitsu Semiconductor LimitedDigital circuits having improved transistors, and methods therefor
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    US-8988153-B1March 24, 2015Suvolta, Inc.Ring oscillator with NMOS or PMOS variation insensitivity
    US-9508728-B2November 29, 2016Mie Fujitsu Semiconductor LimitedCMOS gate stack structures and processes
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    US-9093997-B1July 28, 2015Mie Fujitsu Semiconductor LimitedSlew based process and bias monitors and related methods
    US-8604530-B2December 10, 2013Suvolta, Inc.Electronic devices and systems, and methods for making and using the same
    US-9281248-B1March 08, 2016Mie Fujitsu Semiconductor LimitedCMOS gate stack structures and processes
    US-8273617-B2September 25, 2012Suvolta, Inc.Electronic devices and systems, and methods for making and using the same
    US-8976575-B1March 10, 2015Suvolta, Inc.SRAM performance monitor
    US-9812550-B2November 07, 2017Mie Fujitsu Semiconductor LimitedSemiconductor structure with multiple transistors having various threshold voltages
    US-9093550-B1July 28, 2015Mie Fujitsu Semiconductor LimitedIntegrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
    US-9268885-B1February 23, 2016Mie Fujitsu Semiconductor LimitedIntegrated circuit device methods and models with predicted device metric variations
    US-9385047-B2July 05, 2016Mie Fujitsu Semiconductor LimitedIntegrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
    US-8847684-B2September 30, 2014Suvolta, Inc.Analog circuits having improved transistors, and methods therefor
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    US-8653604-B1February 18, 2014Suvolta, Inc.Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
    US-7652947-B2January 26, 2010International Business Machines CorporationBack-gate decode personalization
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    US-9741428-B2August 22, 2017Mie Fujitsu Semiconductor LimitedIntegrated circuit devices and methods
    US-8994415-B1March 31, 2015Suvolta, Inc.Multiple VDD clock buffer
    US-9006843-B2April 14, 2015Suvolta, Inc.Source/drain extension control for advanced transistors
    US-9385121-B1July 05, 2016Mie Fujitsu Semiconductor LimitedTipless transistors, short-tip transistors, and methods and circuits therefor
    US-8686511-B2April 01, 2014Suvolta, Inc.Source/drain extension control for advanced transistors
    US-8816754-B1August 26, 2014Suvolta, Inc.Body bias circuits and methods
    US-9418987-B2August 16, 2016Mie Fujitsu Semiconductor LimitedTransistor with threshold voltage set notch and method of fabrication thereof
    US-9514940-B2December 06, 2016Mie Fujitsu Semiconductor LimitedReducing or eliminating pre-amorphization in transistor manufacture
    US-6670655-B2December 30, 2003International Business Machines CorporationSOI CMOS device with body to gate connection
    US-8811068-B1August 19, 2014Suvolta, Inc.Integrated circuit devices and methods
    US-9793172-B2October 17, 2017Mie Fujitsu Semiconductor LimitedReducing or eliminating pre-amorphization in transistor manufacture
    US-6784496-B1August 31, 2004Texas Instruments IncorporatedCircuit and method for an integrated charged device model clamp
    US-8819603-B1August 26, 2014Suvolta, Inc.Memory circuits and methods of making and designing the same
    US-8404551-B2March 26, 2013Suvolta, Inc.Source/drain extension control for advanced transistors
    US-8629016-B1January 14, 2014Suvolta, Inc.Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
    US-9276561-B2March 01, 2016Mie Fujitsu Semiconductor LimitedIntegrated circuit process and bias monitors and related methods
    US-9231541-B2January 05, 2016Mie Fujitsu Semiconductor LimitedAnalog circuits having improved transistors, and methods therefor
    US-9184750-B1November 10, 2015Mie Fujitsu Semiconductor LimitedDigital circuits having improved transistors, and methods therefor
    US-8530286-B2September 10, 2013Suvolta, Inc.Low power semiconductor transistor structure and method of fabrication thereof
    US-8895327-B1November 25, 2014Suvolta, Inc.Tipless transistors, short-tip transistors, and methods and circuits therefor
    US-8563384-B2October 22, 2013Suvolta, Inc.Source/drain extension control for advanced transistors
    US-8599623-B1December 03, 2013Suvolta, Inc.Circuits and methods for measuring circuit elements in an integrated circuit device
    US-8999861-B1April 07, 2015Suvolta, Inc.Semiconductor structure with substitutional boron and method for fabrication thereof
    US-8637955-B1January 28, 2014Suvolta, Inc.Semiconductor structure with reduced junction leakage and method of fabrication thereof
    US-7750682-B2July 06, 2010International Business Machines CorporationCMOS back-gated keeper technique
    US-8569128-B2October 29, 2013Suvolta, Inc.Semiconductor structure and method of fabrication thereof with mixed metal types
    US-9196727-B2November 24, 2015Mie Fujitsu Semiconductor LimitedHigh uniformity screen and epitaxial layers for CMOS devices
    US-9680470-B2June 13, 2017Mie Fujitsu Semiconductor LimitedDigital circuits having improved transistors, and methods therefor
    US-2009224803-A1September 10, 2009International Business Machines CorporationCmos back-gated keeper technique
    US-8735987-B1May 27, 2014Suvolta, Inc.CMOS gate stack structures and processes
    US-8796048-B1August 05, 2014Suvolta, Inc.Monitoring and measurement of thin film layers
    US-9111785-B2August 18, 2015Mie Fujitsu Semiconductor LimitedSemiconductor structure with improved channel stack and method for fabrication thereof
    US-9299801-B1March 29, 2016Mie Fujitsu Semiconductor LimitedMethod for fabricating a transistor device with a tuned dopant profile
    US-8883600-B1November 11, 2014Suvolta, Inc.Transistor having reduced junction leakage and methods of forming thereof
    US-8806395-B1August 12, 2014Suvolta, Inc.Porting a circuit design from a first semiconductor process to a second semiconductor process
    US-8863064-B1October 14, 2014Suvolta, Inc.SRAM cell layout structure and devices therefrom
    US-8767789-B2July 01, 2014The Uab Research FoundationMid-IR microchip laser: ZnS:Cr2+ laser with saturable absorber material
    US-8759872-B2June 24, 2014Suvolta, Inc.Transistor with threshold voltage set notch and method of fabrication thereof
    US-9496261-B2November 15, 2016Mie Fujitsu Semiconductor LimitedLow power semiconductor transistor structure and method of fabrication thereof
    US-8995204-B2March 31, 2015Suvolta, Inc.Circuit devices and methods having adjustable transistor body bias
    US-9319013-B2April 19, 2016Mie Fujitsu Semiconductor LimitedOperational amplifier input offset correction with transistor threshold voltage adjustment
    US-9865596-B2January 09, 2018Mie Fujitsu Semiconductor LimitedLow power semiconductor transistor structure and method of fabrication thereof
    US-8877619-B1November 04, 2014Suvolta, Inc.Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
    US-9508800-B2November 29, 2016Mie Fujitsu Semiconductor LimitedAdvanced transistors with punch through suppression
    US-9583484-B2February 28, 2017Mie Fujitsu Semiconductor LimitedTipless transistors, short-tip transistors, and methods and circuits therefor
    US-9431068-B2August 30, 2016Mie Fujitsu Semiconductor LimitedDynamic random access memory (DRAM) with low variation transistor peripheral circuits
    US-8461875-B1June 11, 2013Suvolta, Inc.Digital circuits having improved transistors, and methods therefor
    US-9224733-B2December 29, 2015Mie Fujitsu Semiconductor LimitedSemiconductor structure and method of fabrication thereof with mixed metal types
    US-8975128-B2March 10, 2015Suvolta, Inc.Electronic devices and systems, and methods for making and using the same
    US-9105711-B2August 11, 2015Mie Fujitsu Semiconductor LimitedSemiconductor structure with reduced junction leakage and method of fabrication thereof
    US-2009295432-A1December 03, 2009International Business Machines CorporationCmos back-gated keeper technique
    US-8645878-B1February 04, 2014Suvolta, Inc.Porting a circuit design from a first semiconductor process to a second semiconductor process
    US-9070477-B1June 30, 2015Mie Fujitsu Semiconductor LimitedBit interleaved low voltage static random access memory (SRAM) and related methods
    US-9236466-B1January 12, 2016Mie Fujitsu Semiconductor LimitedAnalog circuits having improved insulated gate transistors, and methods therefor
    US-8604527-B2December 10, 2013Suvolta, Inc.Electronic devices and systems, and methods for making and using the same
    US-9710006-B2July 18, 2017Mie Fujitsu Semiconductor LimitedPower up body bias circuits and methods
    US-9154123-B1October 06, 2015Mie Fujitsu Semiconductor LimitedBody bias circuits and methods
    US-9112495-B1August 18, 2015Mie Fujitsu Semiconductor LimitedIntegrated circuit device body bias circuits and methods
    US-8377783-B2February 19, 2013Suvolta, Inc.Method for reducing punch-through in a transistor device
    US-2009219778-A1September 03, 2009International Business Machines CorporationBack-gate decode personalization
    US-8421162-B2April 16, 2013Suvolta, Inc.Advanced transistors with punch through suppression
    US-2008020872-A1January 24, 2008Johnson Benjamin JHockey stick
    US-2012224599-A1September 06, 2012The Uab Research FoundationMid-ir microchip laser: zns:cr2+ laser with saturable absorber material
    US-8713511-B1April 29, 2014Suvolta, Inc.Tools and methods for yield-aware semiconductor manufacturing process target generation
    US-8541824-B2September 24, 2013Suvolta, Inc.Electronic devices and systems, and methods for making and using the same
    US-9112484-B1August 18, 2015Mie Fujitsu Semiconductor LimitedIntegrated circuit process and bias monitors and related methods
    US-9299698-B2March 29, 2016Mie Fujitsu Semiconductor LimitedSemiconductor structure with multiple transistors having various threshold voltages
    US-8963249-B1February 24, 2015Suvolta, Inc.Electronic device with controlled threshold voltage
    US-9424385-B1August 23, 2016Mie Fujitsu Semiconductor LimitedSRAM cell layout structure and devices therefrom
    US-7750677-B2July 06, 2010International Business Machines CorporationCMOS back-gated keeper technique
    US-9478571-B1October 25, 2016Mie Fujitsu Semiconductor LimitedBuried channel deeply depleted channel transistor
    US-8748986-B1June 10, 2014Suvolta, Inc.Electronic device with controlled threshold voltage
    US-8916937-B1December 23, 2014Suvolta, Inc.Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
    US-9041126-B2May 26, 2015Mie Fujitsu Semiconductor LimitedDeeply depleted MOS transistors having a screening layer and methods thereof